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Abstract Existing circuit camouflaging techniques to prevent reverse engineering increase circuit-complexity with significant area, energy, and delay penalty. In this paper, we propose an efficient hardware encryption technique with minimal complexity and overheads based on ferroelectric field-effect transistor (FeFET) active interconnects. By utilizing the threshold voltage programmability of the FeFETs, run-time reconfigurable inverter-buffer logic, utilizing two FeFETs and an inverter, is enabled. Judicious placement of the proposed logic makes it act as a hardware encryption key and enable encoding and decoding of the functional output without affecting the critical path timing delay. Additionally, a peripheral programming scheme for reconfigurable logic by reusing the existing scan chain logic is proposed, obviating the need for specialized programming logic and circuitry for keybit distribution. Our analysis shows an average encryption probability of 97.43% with an increase of 2.24%/ 3.67% delay for the most critical path/ sum of 100 critical paths delay for ISCAS85 benchmarks. 

This work proposes a new Ferroelectric FET (FeFET) based Ternary Content Addressable Memory (TCAM) with features of integrated search and read operations (along with write), which we refer to as TCAM-RAM. The proposed memory exploits the unique features of the emerging FeFET technology, such as 3-terminal device design, storage in the gate stack, etc., to achieve the proposed functionality. We also introduce Approximate CAM-RAM, which can quantize the bit vector similarity. All the proposed designs operate without negative voltages. We describe both NAND and NOR variants of CAM design. Our CAM design provides 31% area improvement over the previous FeFET 6T CAM design.